1. Field of the Invention
The present invention generally relates to semiconductor memory devices, and, more particularly, to a non-volatile semiconductor device which is electrically erasable and rewritable.
In recent years, various types of flash EEPROM (hereinafter referred to as "flash memory") have been developed as non-volatile semiconductor memory devices which are electrically erasable and rewritable. In particular, cell-type flash memory (hereinafter referred to as "NAND-type flash memory") has been used for files to store a large amount of data, and its memory capacity has been increasing. As the memory capacity of the NAND-type flash memory has increased, the number of memory cell transistors for storing information in the NAND-type flash memory has also increased. For instance, a flash memory having a 16-Mbit capacity contains 16,777,216 memory cell transistors, and a flash memory having a 64-Mbit capacity contains 67,108,864 memory cell transistors. For such a NAND-type flash memory, a product quality test is performed on every memory cell transistor after the completion of the NAND-type flash memory. The NAND-type flash memory performs erasure by the block, which is a group of memory cell transistors. A block consisting of memory cell transistors judged to be defective through the product quality test is called a bad block (invalid block). Such a bad block might occur during the operation of the flash memory. Once a bad block is spotted, no access is allowed to the bad block. Information indicating whether the blocks are valid or invalid is called block valid/invalid information.
2. Description of the Related Art
FIG. 1 is a block diagram of a conventional NAND-type flash memory. This block diagram includes a row address buffer 10, a column address buffer 12, an address register 14, a select Tr decoder 16, a row address decoder 18, a column address decoder 20, a control and high-voltage circuit 22, a command register 24, a memory cell array 26, a Y gate 28, a sense amplifier 30, a data register 32, and an input/output control circuit 34.
The entire operation of the NAND-type flash memory is controlled by a command signal. The command signal, an address signal, and a data signal are supplied to the input/output control circuit 34 via input/output terminals i/o0 to i/o7. The input/output control circuit 34 sends the supplied command signal, address signal, and data signal to the command register 24, the address register 14, and the data register 32, respectively, in accordance with the combination of control signals supplied to the control and high-voltage circuit 22.
The command register 24 latches the supplied command signal, and supplies the latched command signal to the control and high-voltage circuit 22 at desired timing. The control and high-voltage circuit 22 then decodes the command signal, and outputs a control signal to the row address decoder 18, the memory cell array 26, the sense amplifier 30, or the data register 32, whichever is required to perform a process based on the command signal.
The address register 14 latches the supplied address signal, and supplies the latched address signal to the row address buffer 10 and the column address buffer 12 at desired timing. The row address buffer 10 supplied with the address signal from the address register 14 sends the address signal to the select Tr decoder 16 and the row address decoder 18 at desired timing. The column address buffer 12 supplied with the address signal from the address register 14 sends the address signal to the column address decoder 20 at desired timing.
The select Tr decoder 16 outputs a select transistor control signal SL for controlling select transistors included in the memory cell array 26 based on the address signal. The row address decoder 18 decodes the supplied address signal to output a word line signal WL. In accordance with the select transistor control signal SL and the word line signal WL, a data signal selected from cell blocks constituting the memory cell array 26 is sent to the Y gate 28.
The column address decoder 20 decodes the supplied address signal to output a signal for controlling the Y gate 28. The Y gate 28 selects a necessary data signal from data signals supplied from the memory cell array 26, and supplies the selected data signal to the data register 32 via the sense amplifier 30. The data register 32 latches the data signal supplied through the sense amplifier 30, and then sends the data signal to the input/output control circuit 34 at desired timing. The input/output control circuit 34 sequentially outputs data signals in accordance with a clock signal.
FIG. 2 is a timing chart of a data signal reading operation of the NAND-type flash memory of FIG. 1. In the following, signals provided with "/" are negative logic signals, and the other signals are positive logic signals.
When a chip enable signal /CE is inputted into the control and high-voltage circuit 22, a command signal, address signals, and data signals are supplied to the input/output control circuit 34 based on the timing of a write enable signal /WE. Here, the type of the signal to be supplied to the input/output control circuit 34 is determined in accordance with a command latch enable signal CLE and an address latch enable signal ALE supplied to the control and high-voltage circuit 22. More specifically, a signal supplied to the input/output control circuit 34 at the same time as the command latch enable signal CLE is a command signal, and a signal supplied to the input/output control circuit 34 at the same time as the address latch enable signal ALE is an address signal. Accordingly, a command signal (00H) and address signals (A0 to A22) are supplied to the input/output control circuit 34 in the timing chart of FIG. 2.
Data signals are then read from the memory cell array 26, and are outputted sequentially from the input/output control circuit 34 via the Y gate 28, the sense amplifier 30, and the data register 32, in accordance with the timing of a read enable signal /RE.
In the NAND-type flash memory 1 described above, the management side possesses the block valid/invalid information of the blocks. Therefore, it is necessary to produce a table of the block valid/invalid information for each block. Generally, the block valid/invalid information of each block is coded and written in a predetermined position in each corresponding block. Each block is judged whether it is a bad block from the code written in the predetermined position.
When producing a table of the block valid/invalid information, the management side reads out the data of the memory cells of all the blocks, and produces the table of the block valid/invalid information based on the block valid/invalid information contained in the read data. In accordance with the table of the block valid/invalid information, the management side disables access to bad blocks. The table of the block valid/invalid information is updated when a new bad block occurs during an operation of the NAND-type flash memory 1.
In the above conventional structure, however, it is necessary to read out the data of all the blocks to produce the table of the block valid/invalid information. Generally, the NAND-type flash memory is read by the page, for instance, which is a unit of data of one word line, and reading one page of data from the memory cells into the data register 32 requires a certain period of time. Accordingly, producing a table of block valid/invalid information for a larger number of blocks takes a longer period of time.
In a case where it takes 600 ps (microseconds) to read the data of one block, for instance, producing a table of block valid/invalid information for 1000 blocks requires at least 600 ms (milliseconds). Also, in a case where the position of the code indicating the block valid/invalid information becomes defective, there is a problem that the block valid/invalid information cannot be correctly recognized.